Modern ICs often interface with complementary metal-oxide semiconductor (CMOS) voltage levels on chips from previous technology generations. In order to interface with such voltage levels, ICs must include output buffers capable of driving high to an output much greater than the source voltage.
Many output buffer circuits are coupled to one or more power supplies and use output drivers to switch an output voltage according to the values of one or more inputs. For example, an output buffer that receives a high voltage (VDDQ) from a first power supply and an internal chip core voltage (VCC) from a second power supply might have p-channel and n-channel output drivers to switch an output voltage according to values of a data input and an enable input. Typically, output buffers have only a single thin gate oxide. The single thin gate oxide becomes overstressed by a gate-drain voltage much above the source voltage. It is often desirable to protect the gate oxides of these output drivers and other components of the output buffer from overstress, breakdown or other damage due to changes in voltage on the output. Typically, the gate oxide of a transistor can withstand DC voltages (VGD.sub.max) only up to approximately VCC plus a transistor threshold voltage (VT), a fact which motivates much of the circuitry of the present invention.
As microelectronic devices become increasingly complex to satisfy additional processing requirements, reducing the failure of devices during operation becomes increasingly important. A known technique for protecting the gate oxide of output drivers includes coupling cascode devices in series with the output drivers, and in a level shifter, to turn off the switching output P-driver. The cascode devices are supposed to prevent their drains from being pulled past their gate potentials and overstressing the gate oxides of neighboring devices. The cascode devices thus shield the gate oxide of the output driver from voltage levels on the output. The gates of the cascode devices are maintained at fixed voltages, such that the voltage across a gate oxide does not exceed the gate oxide's maximum fixed voltage tolerance. Having the cascode devices at fixed voltages, however, is not optimum for performance. For example, the cascode device gates may remain at an intermediate reference voltage between VDDQ and ground and thus provide minimal drive.